1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (LSI), design support apparatus, and test method, particularly to a logic built-in self-test (BIST) circuit, design support apparatus, and test method, and is applied to, for example, a logic system LSI.
2. Description of the Related Art
As one of the test facilitating methods for solving the difficulty of testing a large and complicated LSI, a logic BIST is used. In the logic BIST, the generation of the test pattern given to a block to be tested, and analysis of the test result output from the block to be tested, are all automatically performed in the LSI by a logic circuit constituted in the periphery of the block to be tested.
FIG. 16 shows a connection relationships between an LSI in which is incorporated a general logic BIST circuit by a self-test using a multiple and parallel shift register sequence generator (STUMPS) system, and an external tester.
An LSI 11 includes a BIST control circuit 12, pattern counter 13, shift counter 14, logic circuit 18 including a large number of flip-flop circuits, test pattern generator 19, test result compressor 16, and the like.
The logic circuit 18 includes a plurality of scan chains 17 chain-connected to flip-flops, and is the block to be tested by the logic BIST. The control circuit 12 receives an external input signal 111 for setting a test mode from a tester 15 to set the LSI 11 to the test mode. The control circuit 12 uses output signals of the pattern counter 13 or shift counter 14 to control the block to be tested 18, test pattern generator 19, and test result compressor 16, and performs BIST control.
In the test mode, first after the logic BIST circuit is initialized, the logic BIST is executed. In this case, a test mode signal or BIST clock is supplied from the external input signal 111 via the control circuit 12, or may be directly supplied from the external input signal 111.
During execution of the logic BIST, a test pattern supplied to a scan chain 17 is automatically generated by the test pattern generator 19. Moreover, a test result output from the scan chain 17 is supplied to the test result compressor 16. In this test result compressor 16, the test result is compressed into data (signature) having a specific bit length. This test result compressor 16 supplies a signal 110 indicating a test analysis result of the logic circuit 18 to the LSI external tester 15. The tester 15 judges from the signal indicating the supplied test analysis result whether the logic circuit 18 is functioning correctly or not.
In a test in which the logic BIST circuit is used, the test pattern does not have to be prepared in a memory (not shown) of the tester 15. Therefore, the cost of the tester 15 can be reduced. Moreover, all the operations are performed in the LSI 11 in synchronization with a BIST clock signal. Therefore, when a BIST clock signal having a rate higher than the test operation frequency of the tester 15 is used, a test having a rate higher than that of the test by the tester 15 is possible. Accordingly, a product test in an actual operation can be performed.
Moreover, the test in which the logic BIST circuit is used requires only a small number of external input/output signals. Therefore, it is possible to test a plurality of blocks in parallel, and test time can greatly be reduced.
Furthermore, the test using the logic BIST circuit is not restricted by the number of scan inputs/outputs in accordance with the capability of the tester 15. Therefore, a larger number of scan chains 17 can be constructed as compared with a general scan design. When the number of the scan chains 17 is increased, the scan chain length per scan chain becomes shorter, and the test time can be reduced.
In the logic BIST circuit, in general, a logic circuit which is a test object operates at random. A random-number pattern generator is used as the test pattern generator 19. As this random-number pattern generator 19, a linear feedback shift register (LFSR) is frequently used.
FIG. 17 shows a constitution of an LFSR of five bits as one example of the test pattern generator 19 in FIG. 16.
This LFSR is constituted so that results obtained by calculating outputs 1502, 1505 of a specific register (feedback point) and output 1508 of a final-stage register with an exclusive OR gate 1501 are inputs of a top register 1515, and perform a shift operation in synchronization with the clock signal of a clock signal line 1514.
To use this LFSR as the pattern generator, an initialization operation is necessary, and all bits are set to appropriate initial values. In this initialization operation, the bit is set to the initial value held inside LSI in some case, and set to the initial value from the outside in the other case.
In the initialized LFSR, the values of registers 1515, 1503, 1504, 1506, 1507 are calculated and shifted by the exclusive OR gate 1501 in response to the clock signal. As a result, the values of the registers 1515, 1503, 1504, 1506, 1507 change at random. The random values of the registers are supplied as the random pattern to the block to be tested via output signal lines 1509, 1510, 1511, 1512, 1513.
The result of the test using the above-described test pattern is analyzed by the test result compressor 16 in FIG. 16. This test result compressor 16 is constituted, for example, of a multiple input signature register (MISR). The basic structure of this MISR is the same as that of the LFSR, but different in that the input data is taken in parallel.
FIG. 18 shows the constitution of a five-bit MISR as one example of the test result compressor 16 in FIG. 16.
In this MISR, exclusive OR gates 1610, 1609, 1608, 1607, 1606 are disposed for registers 1611, 1612, 1613, 1614, 1615 of stages. These exclusive OR gates 1610, 1609, 1608, 1607, 1606 calculate output signals of a previous-stage register (additionally, the output signal of the last-stage register 1615 for the exclusive OR gate 1610) and parallel input signals 1601, 1602, 1603, 1604, 1605. This calculation result is supplied and shifted to the respective registers 1611, 1612, 1613, 1614, 1615 in synchronization with the clock signal of a clock signal line 1616. The register 1613 receives a result obtained by calculating the parallel inputs and output signals of the previous-stage register and final-stage register 1615.
Also when this MISR is used as the test result compressor, the initialization is necessary in the same manner as in the LFSR. However, unlike the LFSR, it is also possible to initialize all the bits to “0”.
When the clock signal is supplied to the initialized MISR, the parallel input data 1601, 1602, 1603, 1604, 1605 are taken in and compressed. Finally, data finally left in the register is a compression result. When the compression result is compared with an expected value (hereinafter referred to as the signature) obtained beforehand by calculation, a failure is judged.
As described above, by the test using the logic BIST circuit, presence/absence of a failure in the LSI is judged. As a result, for an LSI having the failure, the failure is sometimes analyzed.
In this case, as described above, since the information indicating the presence/absence of the failure is compressed inside the LSI in the test using the logic BIST circuit, the information necessary for analyzing the failure cannot be obtained as such. The failure analysis requires the information of a test pattern (failure pattern) for detecting the failure and scan flip-flop (failure scan flip-flop) for taking in the influence of the failure. Therefore, it is necessary to obtain this information with an operation different from a usual logic BIST operation.
When the logic BIST circuit is used to analyze the failure, there is a method of dividing the operation for each pattern. Here, one pattern indicates that a logic value captured in parallel by the scan flip-flop is serially shifted out. In general, serial shift out of a n-th pattern and serial shift in of n+1st pattern are simultaneously performed. Therefore, here, a segment of one pattern is set from when the values are captured in parallel until the logic values are serially shifted out.
In this case, the states of a test result analyzer are compared with one another for each pattern, and a pattern in which the expected value differs from the signature is identified. Therefore, the test pattern for detecting the failure is obtained.
Next, to know the position of the failure scan flip-flop, the scan chain 17 of the block to be tested 18 shown in FIG. 16 is switched to a scan test mode.
FIG. 19 shows a constitution example of the scan test mode of the logic BIST circuit shown in FIG. 16.
An LSI to be tested 1701 is switched to the scan test mode by a control signal 1703 from a tester 1710, and a scan chain 1706 is cut off from a test pattern generator 1709 and test result compressor 1705. This scan chain 1706 is connected to one or several scan chains.
A scan input terminal 1708 and scan output terminal 1704 are connected to a scan channel of the tester 1710. In this scan test mode, the test pattern obtained beforehand is scanned in or out from the outside to specify a failure scan flip-flop.
However, when the logic BIST circuit is used to analyze the failure as described above, there are several problems as follows.
That is, an execution result of the tester has to be analyzed in order to obtain the test pattern. In addition to this analysis time, a test time lengthens, because the mode is switched to the scan test mode as shown in FIG. 19 to carry out the test a plurality of times.
Moreover, it is necessary to separately prepare the scan test pattern, and as a problem, a design time required until the scan becomes possible lengthens.
Furthermore, the mode is switched to the scan test mode to carry out the test. Therefore, the failure which can be detected only by a logic BIST operation cannot be analyzed. This is an important problem, when an actual operation rate test is carried out by the logic BIST operation. Therefore, there has been a semiconductor integrated circuit in which during the test performed using the logic BIST circuit, it is possible to output number information of the pattern in which the failure is detected, and further the position information of the scan flip-flop as circumstances demand, and a failure analysis operation can easily be performed outside. Furthermore, to design the logic BIST circuit, there has been a demand for development of a design support apparatus of a semiconductor integrated circuit, which can easily prepare a file. The file includes a correspondence between failure count and failure pattern, in which conversion of the failure count to the failure pattern is possible.